Digital packaging has continued to change into extra complicated with greater gadget rely, greater energy densities and Heterogeneous Integration (HI) changing into extra widespread. Within the cell area, programs that have been as soon as separate elements on a printed circuit board (PCB) have now been relocated together with all their related passive gadgets and interconnects into single System in Package deal (SiP) model subassemblies. Excessive-power computing and information middle packages have seen related tendencies, the place reminiscence has moved right into a single interposer-based built-in bundle. In distinction to the speedy growth and complexity will increase of recent superior packages, the bodily legal guidelines that govern mechanical stress and warmth switch have remained fixed. Whereas packaging materials developments have made nice advances lately, a revolutionary materials doesn’t exist to remove mechanical stresses and thermal considerations.
To information engineering decision-making throughout bundle design, mechanical (each structural and thermal) simulation is an applicable instrument to foretell gadget efficiency, examine gadget failures, discover root causes, and carry out optimization research. This weblog put up will give attention to the distinctive challenges of complicated packages that require excessive simulation constancy and discover two case research the place simulation was used to characterize bundle thermal efficiency.
Case examine 1: Cell market packaging
The primary case examine describes a situation the place a System in Package gadget is meant for the cell market. The bundle is predicted to be sandwiched between two stacked printed circuit boards (PCBs), which limits the choices out there to take away warmth from the bundle: warmth have to be performed to the PCB and restricted complete bundle thickness precludes a top-side copper warmth spreader.
The next enhancements in a Double-Sided Molded Ball Grid Array (DSMBGA) have been examined: high- thermal conductivity epoxy molding compound (EMC); changing the BGA with giant copper (Cu) posts; and a system-level underfill that seals the hole between a bottom-side uncovered die and the PCB (see determine 1). Of those choices, solely the system-level underfill offered important thermal enchancment: roughly 10% discount in thermal resistance from junction to ambient (ΘJA) in a regular JEDEC still-air atmosphere. Cu put up enhancements have been negligible, and the high-thermal conductivity EMC resulted in lower than 1% enchancment (see determine 2). This simulation was carried out with Siemens Simcenter Flotherm.
Fig. 1: BGA format distinction between a typical BGA gadget (A) and a DSMBGA gadget (B) with lively elements and dies on the underside facet of the substrate. (C) Reveals a consultant cross-section of a DSBGA gadget.
Fig. 2: (A) Location of board-level underfill beneath dies on backside facet of substrate. (B) Simulation temperature distinction between non-underfilled (high) and underfilled (backside) packages. Coloration scale is constant between photographs. (C) Simulation consequence chart with varied underfill thermal conductivities.
Case examine 2: Massive physique bundle
The second case examine on this presentation is a coupled structural-thermal simulation of a giant physique High-Density Fan-Out (HDFO) bundle with a central application-specific built-in circuit (ASIC) and a number of excessive bandwidth memory (HBM) modules (see determine 3). Most thermal simulations assume (for the sake of pace and ease) a relentless thermal interface materials (TIM) bond line thickness between the highest of the ASIC/HBM module and the underside of the lid. On this examine it was fascinating to have a greater understanding of how variations in bond line thickness (because of warpage) throughout the ASIC and module space might have an effect on thermal efficiency of the bundle.
Fig. 3: Massive-Physique HDFO Mannequin. Quarter symmetry view (left). Expanded view (proper) with lid hidden to point out the ASIC+6 HBM HDFO module.
A 63 x 63 mm HDFO bundle was first simulated in Ansys Icepak to generate a “power-on” temperature profile that could possibly be utilized to the construction in Ansys Workbench Mechanical. This temperature profile had two functions: to use as a temperature situation throughout the structural mannequin to create stresses and calculate deformation of the mannequin as a result of totally different coefficients of thermal growth for every materials; and second, to calculate a lid-top and substrate-bottom temperature boundary situations to use within the Ansys Mechanical steady-state thermal simulations of the deformed geometry and assorted TIM bondline (see determine 4).
Fig. 4: (Clockwise, from high left) Ansys Mission Schematic, exhibiting linked subsystems that couple thermal and structural fashions. Package deal Warpage, 20°C, dead-bug view (trying on the backside of the substrate). Package deal warpage with “Energy-On” thermal gradient utilized, dead-bug view (similar shade scale as 20°C warpage). Temperature profile boundary situation as imported from Icepak.
The deformed geometry (calculated at each 20°C for room temperature warpage baseline and on the Icepak-simulated “power-on” temperature) was then used because the geometry for thermal fashions. Variations of the lively floor junction temperature, measured relative to an undeformed baseline, have been calculated, and reported throughout the die floor (see determine 5).
Fig. 5: Temperature consequence chart of the varied simulated ASIC temperatures. Error bars characterize complete temperature vary throughout the die face.
The Ansys mechanical thermal mannequin experiences a mean ASIC temperature of 88.9°C throughout the die face, with a most of 92.6° and a minimal of 82.8°C (for a temperature delta throughout the die of 9.7°C). The 20°C form mannequin experiences 86.0°C common die temperature, a most of 89.1°C and a minimal of 81.4°C (for a temperature delta of seven.7°C throughout the die). The “Energy-On” form mannequin experiences 86.3°C common die temperature, a most of 89.4°C and a minimal of 81.4°C (for a temperature delta of 8.0°C throughout the die).
Die temperatures within the fashions that account for bond line thickness (BLT) variation look like extra constant (decrease delta throughout the die) because of thinner bond line on the middle of the module and thicker bond line on the corners of the module (relative to a 50 µm BLT baseline). This case examine ends in a greater understanding of the uncertainty of future fashions.
Nathan Whitchurch is a senior employees engineer supporting packaging and mechanical simulation at Amkor. Previous to coming into the electronics packaging discipline, Whitchurch labored on tasks together with vehicle-mounted pc rack enclosures, radio thermal design, datacenter thermal evaluation, and programs integration. He gives system-level context and understanding to mechanical simulations on the bundle degree. Whitchurch holds a BS diploma in mechanical engineering from the College of Southern California.